The present invention relates to the field of semiconductor memory devices and, more particularly to a method of reducing trapped holes in a tunnel oxide layer of flash memory cells.
A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is the flash EEPROM device (also referred to as xe2x80x9cflash memoryxe2x80x9d).
Each nonvolatile memory device has its own unique characteristics. For example, the memory cells of an EPROM device are erased using an ultraviolet light, while the memory cells of an EEPROM device are erased using an electrical signal. In a conventional flash memory device blocks of memory cells are simultaneously erased (what has been described in the art as a xe2x80x9cflash-erasurexe2x80x9d). The memory cells in a ROM device, on the other hand, cannot be erased at all. EPROMs, EEPROMs and flash memory are commonly used in computer systems that require reprogrammable nonvolatile memory.
A conventional flash memory device includes a plurality of memory cells, each cell is provided with a floating gate covered with an insulating layer. There is also a control gate which overlays the insulating layer. Below the floating gate is another insulating layer sandwiched between the floating gate and the cell substrate. This insulating layer is an oxide layer and is often referred to as the tunnel oxide. The substrate contains doped source and drain regions, with a channel region disposed between the source and drain regions.
In a flash memory device, a charged floating gate represents one logic state, e.g., a logic value xe2x80x9c0xe2x80x9d, while a non-charged floating gate represents the opposite logic state e.g., a logic value xe2x80x9c1xe2x80x9d. The flash memory cell is programmed by placing the floating gate into one of these charged states. Charges may be injected or written on to the floating gate by any number of methods, including e.g., avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron (CHE) injection. The floating gate may be discharged or erased by any number of methods including e.g., Fowler-Nordheim tunneling.
During a typical erase operation by Fowler-Nordheim tunneling, charges stored on the floating gate are driven out of the floating gate, through the tunnel oxide, and in to the source region. This tunneling of electrons may be achieved by applying a relatively low positive voltage (e.g., approximately 5 volts) to the source region and a relatively large negative voltage (e.g., xe2x88x928 to xe2x88x9212 volts) to the control gate. The substrate is usually grounded and the drain region is usually left floating. These voltages create an electric field between the floating gate and the source region, which induces the electrons previously stored on the floating gate to tunnel through the tunnel oxide to the source region.
Unfortunately, the charge retention property of flash memory cells becomes degraded after a number of programming and erase cycles. This degradation is believed to be caused by the presence of holes that become trapped in the tunnel oxide after an erase operation. After each erase operation, more holes become trapped within the tunnel oxide. It is believed that these trapped holes induce a localized reduction of a potential barrier that is used to prevent electrons stored on the floating gate from escaping through the tunnel oxide. The sites in the tunnel oxide with the reduced barrier essentially create a path for the stored electrons to leak or escape from the floating gate (referred to herein as a xe2x80x9cleakage pathxe2x80x9d).
The leakage path leads to a gradual discharging of the floating gate during times when the floating gate is expected to retain its charge. Also, the reduced barrier for tunneling can induce faster, erratic erasure for the relevant cells in a subsequent erase operation, leading to excess column current and read and/or program failure. Both charge leakage and erratic erasure adversely impact the program/erase cycling performance, charge retention and overall endurance of the flash memory cell. The term xe2x80x9ccyclexe2x80x9d or xe2x80x9ccyclingxe2x80x9d typically refers to the sequence of one program operation and one erase operation. Data retention is impacted because data cannot be stored at the desired potential. Endurance is impacted because after a number of cycles the flash memory cells will no longer be able to be programmed with a charge suitable for the logic levels associated with a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Thus, there is a desire and need for a method of erasing flash memory cells that substantially reduces trapped holes within the tunnel oxide of the flash memory device.
There have been attempts to reduce the number of trapped holes within the tunnel oxide of the flash memory cell. One technique is to reduce the number of holes injected into the tunnel oxide during the erase operation. This can be achieved by e.g., reducing the voltages used during the erase operation. These techniques, however, typically reduce the speed of the erase operation. Moreover, holes that are injected into the tunnel oxide may still become trapped, which eventually degrades the performance and endurance of the flash memory device. Thus, there is a desire and need for a method of erasing flash memory cells that substantially improves the overall performance and endurance of the flash memory device without adversely impacting the speed of the erase operation.
The present invention provides a method of erasing memory cells within a flash memory device that substantially reduces trapped holes within the tunnel oxide of the device.
The present invention also provides a method of erasing flash memory cells that substantially improves the overall performance and endurance of the flash memory device without adversely impacting the speed of the erase operation.
The above and other features and advantages are achieved by a method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide. The method uses an erase operation that over-erases each memory cell undergoing the erase operation. A cell healing operation is performed on all of the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.